module ram #(
    parameter Bits = 128,       //ram 默认规格128b*64=1KB
    parameter Word_Depth = 64,
    parameter Add_Width = 6
) (
    input clk,
    input cen,              //使能信号，低电平有效
    input wen,              //写使能，低电平有效
    input [Add_Width-1:0] a,//地址端
    input [Bits-1:0] d,     //数据输入端
    output reg [Bits-1:0] q 
);

reg [Bits-1:0] mem[0:Word_Depth-1];
integer i;

initial begin
    for(i=0; i<Word_Depth; i=i+1) begin
        mem[i] = 'b0;
    end
end

always@(posedge clk) begin
    if(!cen) begin
        if(wen)//wen=1, read
            q <= mem[a];
        else //wen=0, write
            mem[a] <= d;
    end
end

endmodule